Not Applicable.
The present invention relates to the field of data communications, and more particularly, to the field of framing data in a communications system.
In data communications, data is generally transmitted in a serial communications format through current networks. It is often the case that the data to be transmitted between two data endpoints is packaged according to specific data communications protocols to facilitate the transmission across the particular network in question. This packaging may include the addition of network management and other information such as as headers and trailers to the data to facilitate transmission based upon the dictates of the particular protocol employed. Such packaging is generally termed xe2x80x9cframingxe2x80x9d in the art.
Some of these protocols may include, for example, data transmission using time division multiplexing (TDM) approaches such T1 and E1 standards known in the art. Other example standards may include high-level data link control (HDLC) or asynchronous transfer mode (ATM). Each of these protocols have their own applications and goals in terms of history, performance, error-immunity, flexibility, and other factors. Consequently, each of these protocols employ framing procedures by which data is packaged for transmission across the various networks employed. These protocols are generally incompatible and require translation or conversion to transmit data in a transmission link that employs two or more protocols in two or more different segments.
The conversion from one protocol to another requires specific framing technology to accomplish the task. With a myriad of standards between which conversion is possible, many different dedicated protocol conversion units have been developed to accomplish the specific conversion tasks presented. The typical protocol conversion unit is labeled xe2x80x9cdedicatedxe2x80x9d above because such units generally employ dedicated circuits which are capable only of performing the conversion from one specific protocol to another. The result of this fact is a multitude of protocol conversion units on the market to accomplish the individual conversion tasks, thereby diminishing efficiencies to be obtained by mass production.
It is also the case that new communications standards are developed as data communication technology develops over time. Often times, a particular standard may be in flux while discussion ensues among those skilled in the art until agreement on concrete provisions articulating a standard is reached. Consequently, it is difficult to develop data communications technology that employs an up and coming standard until the standard is settled. In the competitive world of data communications technology production, it is desirable to produce products to meet these new standards as quickly as is possible after a standard is finalized so as to compete in the marketplace.
An objective of the present invention is to provide for a data communications protocol conversion unit which can achieve protocol conversions between any number of protocols to obtain the efficiencies of mass production and feature the flexibility allowing the unit to be quickly adapted to new data communications protocols as they develop.
In furtherance of this and other objectives, the present invention entails a programmable data communications protocol conversion unit (PCU) according to embodiments of the present invention. The PCU is a processor circuit which includes a means for performing full parallel, partial parallel, and bit data transfers. In particular, a bit assembly register is employed to assemble partial parallel data blocks which comprise data with a number of bits that is equal to or less than the order of the data bus of the PCU. The bit assembly register further includes the capability of writing the partial parallel data block to predetermined locations using a full parallel transfer and a shadow bus with bits indicating the validity of the particular bits in the data block transferred. The particular circuits receiving partial parallel writes include a register for receiving data and a register for receiving the corresponding shadow bits. Invalid data, that is, data with the associated shadow bit set to zero, that is written to these registers is ignored while valid data is shifted accordingly, for example, out to a serial interface.
The PCU further includes a task specific circuit for performing bit alignment and other tasks and a task specific circuit for generating cyclic redundancy check (CRC) data. The later circuit can create CRC data for any number of protocols as the circuit is highly configurable with a bit shift register of varying lengths.
In accordance with another aspect of the present invention, a method is provided for processing data in a processor unit, comprising the steps of performing a bit write operation allowing the processor to write a single predefined data bit to a target register, and performing a partial parallel data transfer allowing the processor to transfer a predefined partial parallel data value to a target register. The step of performing the bit write operation further comprises the step of coupling an instruction decoder to a plurality of input registers with a bit bus, the input registers being associated with a plurality of logical circuits. The method may also include the steps of translating a full parallel data transfer into a partial parallel data transfer, transferring the partial parallel data to the target register, and indicating the validity of data bits in the partial parallel data.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention, as defined by the claims.